
Pier Andrea Francese
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy,... | Zurich, Zurich, Switzerland
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Pier Andrea Francese’s Emails pi****@ib****.com
Pier Andrea Francese’s Phone Numbers No phone number available.
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Pier Andrea Francese’s Location Zurich, Zurich, Switzerland
Pier Andrea Francese’s Expertise Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.
Pier Andrea Francese’s Current Industry Ibm
Pier
Andrea Francese’s Prior Industry
Teradyne
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Philips Semiconductors
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Eth Zurich
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National Semiconductor
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Ibm
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Work Experience

Ibm
Principal Research Staff Member
Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Ibm
Research Staff Member
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
National Semiconductor
Principal Analog Ic Designer
Tue Nov 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Eth Zurich
Research Assistant
Fri Sep 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Philips Semiconductors
Ic Design/Test Engineer
Sat Mar 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Teradyne
Test Application Engineer
Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)