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Ping-Han Tsai

I am in SOC chip/block implementation from gate level netlist to GDS tape-out. My passion lies in making... | Austin, Texas, United States

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Ping-Han Tsai’s Location Austin, Texas, United States

Ping-Han Tsai’s Expertise I am in SOC chip/block implementation from gate level netlist to GDS tape-out. My passion lies in making advance technology chip tape-out successfully. Guide customer toward correct path to tape-out. 7 years experience in tape-out with muilt-million gates count SOC design in 16/12/10/7//5/3 nm technology node. Solid skill set of Candence/Synsopsys/Metnor EDA tools. Capable of executing P&R, CTS, timing closure and physical verification. Experience in CAD methodology and problem, solving skills. Familiar with Verilog, Per/Tcl, Python. Experience list: 1. experiences in 16/12/10/7/5/3nm technology node 2. SoC block physical design for macro placement, multiple power domains design, ICC/innovus pnr implementation, and STA/DRC/LVS/Antenna/EMIR/SignalEM/Noise fixing 3. rtl-to-gds implementation + PV/STA clean + formality/Verdi/VCS verification on BIST circuit 4. Chip PV integration/verification 5. SPICE simulation for analog circuit and timing signoff U.S. Permanent Resident

Ping-Han Tsai’s Current Industry 台灣積體電路製造股份有限公司

Ping-Han Tsai’s Prior Industry
Tsmc | 台灣積體電路製造股份有限公司

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Work Experience

台灣積體電路製造股份有限公司

Principal Engineer

Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Tsmc

Senior Engineer

Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Tsmc

Engineer

Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

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Ping-Han Tsai Email Addresses

[email protected] Email

Ping-Han Tsai Phone Number

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FAQ About Ping-Han Tsai

Ping-Han Tsai is located at
Austin, Texas, United States

Ping-Han Tsai is a
I am in SOC chip/block implementation from gate level netlist to GDS tape-out. My passion lies in making advance technology chip tape-out successfully. Guide customer toward correct path to tape-out. 7 years experience in tape-out with muilt-million gates count SOC design in 16/12/10/7//5/3 nm technology node. Solid skill set of Candence/Synsopsys/Metnor EDA tools. Capable of executing P&R, CTS, timing closure and physical verification. Experience in CAD methodology and problem, solving skills. Familiar with Verilog, Per/Tcl, Python. Experience list: 1. experiences in 16/12/10/7/5/3nm technology node 2. SoC block physical design for macro placement, multiple power domains design, ICC/innovus pnr implementation, and STA/DRC/LVS/Antenna/EMIR/SignalEM/Noise fixing 3. rtl-to-gds implementation + PV/STA clean + formality/Verdi/VCS verification on BIST circuit 4. Chip PV integration/verification 5. SPICE simulation for analog circuit and timing signoff U.S. Permanent Resident 台灣積體電路製造股份有限公司

Ping-Han Tsai currently works in the
台灣積體電路製造股份有限公司

Ping-Han Tsai specializes in
I am in SOC chip/block implementation from gate level netlist to GDS tape-out. My passion lies in making advance technology chip tape-out successfully. Guide customer toward correct path to tape-out. 7 years experience in tape-out with muilt-million gates count SOC design in 16/12/10/7//5/3 nm technology node. Solid skill set of Candence/Synsopsys/Metnor EDA tools. Capable of executing P&R, CTS, timing closure and physical verification. Experience in CAD methodology and problem, solving skills. Familiar with Verilog, Per/Tcl, Python. Experience list: 1. experiences in 16/12/10/7/5/3nm technology node 2. SoC block physical design for macro placement, multiple power domains design, ICC/innovus pnr implementation, and STA/DRC/LVS/Antenna/EMIR/SignalEM/Noise fixing 3. rtl-to-gds implementation + PV/STA clean + formality/Verdi/VCS verification on BIST circuit 4. Chip PV integration/verification 5. SPICE simulation for analog circuit and timing signoff U.S. Permanent Resident