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Po-Shao Cheng

A passionate Design Verification Engineer with strong technical background in using SystemVerilog and UVM. Current role responsibilities include... | Cambridge, England, United Kingdom

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Po-Shao Cheng’s Location Cambridge, England, United Kingdom

Po-Shao Cheng’s Expertise A passionate Design Verification Engineer with strong technical background in using SystemVerilog and UVM. Current role responsibilities include developing verification components for verifying complex and safety critical FPGA designs within the defence and aerospace industry. Deeply involved in key stages of the verification process and project lifecycle with the ability to own sophisticated verification tasks. Graduated from the University of Bristol with a MEng degree in Electrical and Electronics Engineering.

Po-Shao Cheng’s Current Industry Siemens Digital Industries Software

Po-Shao Cheng’s Prior Industry
Ming Yuan Jewellery Shop | Fullconn | Bae Systems | Siemens Digital Industries Software

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Work Experience

Siemens Digital Industries Software

Senior Verification Engineer

Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Bae Systems

Senior Verification Engineer

Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Bae Systems

Design Verification Engineer

Tue Sep 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Bae Systems

Graduate Hardware Engineer

Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Fullconn

Assistant Engineer

Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Ming Yuan Jewellery Shop

Sales Assistant

Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

Po-Shao Cheng Email Addresses

po****@ba****.com Work Email

po****@ba****.com Personal Email

FAQ About Po-Shao Cheng

Po-Shao Cheng is located at
Cambridge, England, United Kingdom

Po-Shao Cheng is a
A passionate Design Verification Engineer with strong technical background in using SystemVerilog and UVM. Current role responsibilities include developing verification components for verifying complex and safety critical FPGA designs within the defence and aerospace industry. Deeply involved in key stages of the verification process and project lifecycle with the ability to own sophisticated verification tasks. Graduated from the University of Bristol with a MEng degree in Electrical and Electronics Engineering. Siemens Digital Industries Software

Po-Shao Cheng currently works in the
Siemens Digital Industries Software

Po-Shao Cheng specializes in
A passionate Design Verification Engineer with strong technical background in using SystemVerilog and UVM. Current role responsibilities include developing verification components for verifying complex and safety critical FPGA designs within the defence and aerospace industry. Deeply involved in key stages of the verification process and project lifecycle with the ability to own sophisticated verification tasks. Graduated from the University of Bristol with a MEng degree in Electrical and Electronics Engineering.

Po-Shao Cheng speaks the following languages:
No languages available.

Po-Shao Cheng has prior experience in the following industries:
Bae Systems , Bae Systems , Bae Systems , Fullconn , Ming Yuan Jewellery Shop

Po-Shao Cheng has the following professional experience:
Siemens Digital Industries Software , Bae Systems , Bae Systems , Bae Systems , Fullconn , Ming Yuan Jewellery Shop .