
Pranay Samanta
I am a VLSI engineer with 9.5 years of experience in functional verification field and additional 11 months... | Intel, NO 17, India
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Pranay Samanta’s Location Intel, NO 17, India
Pranay Samanta’s Expertise I am a VLSI engineer with 9.5 years of experience in functional verification field and additional 11 months of internship experience. I'm a highly reliable person who can always be trusted to come up with a solution of issues very quickly and efficiently. So provide me an issue, I will provide you the bug which is causing the issue in the fastest possible manner. In my work ethics there is no option for failure but I acknowledge my fair share of mistake and failure and accept as a positive experience. Debugging is my strength, love and passion. I love finding out bugs from design rapidly and provide the solution to designers - which I feel the most important aspect for verification in modern complex designs due to squeezing of time to market. Quicker the company is able to unveil the product in market, more profitable the company would be than its' competitors - that's why I believe I can be an asset to the company I'm working for. Specialties: Rapid and effective Debugging User friendly coding with indentations and comments UVM OVM APB AXI JESD JTAG PHY SERDES IP verification SS verification SoC verification FW verification RAL and Register verification System Verilog Test planning ECC verification 100% Coverage closure (Functional and Code) - No compromise GLS zero-delay GLS with SDF - Bugs are found on GLS too UPF simulation (little) Scripting Sharing the knowledge with colleagues and ever smiling attitude
Pranay Samanta’s Current Industry Intel
Pranay
Samanta’s Prior Industry
Iiit Delhi
|
Stmicroelectronics
|
Intel
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Work Experience

Intel
Soc Design Verification Engineer
Fri Apr 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Stmicroelectronics
Design Engineer
Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Intern
Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Iiit Delhi
Teaching Assistant
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)