
Pravin Gavate
Over 15+ years of experience in Pre Si Validation / Post Si Validation, FPGA Prototyping, Synopsys Zebu based... | Bengaluru, Bengaluru, India
*50 free lookup(s) per month.
No credit card required.
Pravin Gavate’s Emails pr****@in****.com
Pravin Gavate’s Phone Numbers No phone number available.
Social Media
Pravin Gavate’s Location Bengaluru, Bengaluru, India
Pravin Gavate’s Expertise Over 15+ years of experience in Pre Si Validation / Post Si Validation, FPGA Prototyping, Synopsys Zebu based SoC Emulation, FPGA based Design/Verification, Embedded System Design o Pre and Post Silicon Validation o Multiple Arm based Multi Million Gate SoC Validation in Multi FPGA partitioned environment o IP Validation o RTL coding and verification using Verilog and VHDL o HDL/HVL: Verilog, System Verilog, VHDL o Computer Languages: C, C++, Assembly, Python o Protocols - CXL, SAS, SATA, PCI Express, DDR, AXI, SDIO, Graphics Pipeline o Design Engineer Customer Support of storage RAID controller and Expander ICs o Acquainted with schematic capture, PCB design, signal integrity and design tools such as orcad and PADS
Pravin Gavate’s Current Industry Intel
Pravin
Gavate’s Prior Industry
Intel
|
Id Technology
|
Aftek
|
Mindtree
|
Lsi
|
Nvidia
|
Aricent
|
Sevitech Systems
Not the Pravin Gavate you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Intel
Soc Emulation Lead
Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Sevitech Systems
Technical Manager
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Aricent
Technical Lead
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Nvidia
Senior Design Engineer
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi
Senior Design Engineer
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Mindtree
Module Lead R/D Services
Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Aftek
Hardware Design Engineer
Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Id Technology
Vlsi Design Engineer
Sun Feb 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Soc Emulation Lead
— Present