Qian Yao

Qian Yao

ASIC/FPGA design and verification Skill: RTL design using Verilog, FPGA Synthesis with Snopsys Synplify, FPGA P&R build using Xilinx... | United States

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Work Experience

Qualcomm

Senior Staff Design Engineer

Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Maxim Integrated

Principal Design Engineer

Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Silicon Image

Staff Engineer

Thu Nov 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Maxim Integrated

Sr. Member of Techincal Staff

Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Astute Networks

Senior Design Engineer

Wed Aug 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Lsi Logic

Senior Design Engineer

Sat Jul 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

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