Quincy Chiu

Quincy Chiu

Apply semiconductor fabrication process knowledge to identify physical defects and process marginality in order to improve product yield.... | Portland, Oregon, United States

*50 free lookup(s) per month.

No credit card required.

Quincy Chiu’s Emails

Quincy Chiu’s Phone Numbers

Social Media

Quincy Chiu’s Location

Quincy Chiu’s Expertise

Quincy Chiu’s Current Industry

Quincy Chiu’s Prior Industry

Not the Quincy Chiu you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Intel

Data Analyst & Test Architect

Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

DTD Yield Analysis Manager

Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

PTD Yield Analysis Manager

Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

PTD Yield Analysis Engineer

Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Yield Analysis Engineer

Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Wafertech

Sr. Product Engineer

Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Wafertech

Yield Enhancement Engineer

Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Us Army Corps Of Engineers

Student Engineer

Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

No languages available.