
Rahul Prabhu
Present: Physical Design Engineer at Apple Inc. Past: SoC Physical Design Engineer at Intel Corp. Worked on high-speed clock distribution and... | Folsom, California, United States
*50 free lookup(s) per month.
No credit card required.
Rahul Prabhu’s Emails ra****@cy****.com
Rahul Prabhu’s Phone Numbers No phone number available.
Social Media
Rahul Prabhu’s Location Folsom, California, United States
Rahul Prabhu’s Expertise Present: Physical Design Engineer at Apple Inc. Past: SoC Physical Design Engineer at Intel Corp. Worked on high-speed clock distribution and methodology, PPA convergence for data-path logic and register file design. Graduate student in Electrical and Electronics Engineering at the University of Minnesota, Twin Cities specializing in VLSI Design. Former Product and Test Engineer at Cypress Semiconductors, Bangalore from 2012-2015. Worked on ATE test program development for IC test and characterization, post-silicon debug and full-chip state-transition validation of SoCs based on the PSoC (programmable system-on-chip) platform. Languages: C, C++, Verilog HDL, Perl, SKILL, Tcl, MATLAB, SQL Operating Systems: Windows XP/7/10, Linux Full Custom Design Tools: Cadence Virtuoso, Synopsys HSPICE, CosmosScope and Mentor Graphics Calibre Semi-Custom Design Tools: Synopsys Design Compiler, Formality, TetraMax, VCS, DVE and IC Compiler Others: SimpleScalar, CACTI 6.5, Cypress PSoC Creator, Xilinx ISE 12.1 Hardware Tools: Boards: Xilinx Virtex-4, PSoC4A-BLE Pioneer Kit ATE: Teradyne Nextest Magnum-I, HP Versatest VT3300 Bench char/test: Oscilloscopes, Logic Analyzers, Function generators, Digital Multi-meters, Power Supplies.
Rahul Prabhu’s Current Industry Apple
Rahul
Prabhu’s Prior Industry
Persistent Systems
|
Cypress Semiconductor
|
Intel
|
Apple
Not the Rahul Prabhu you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Apple
Physical Design Engineer
Mon Feb 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
SoC Design Engineer
Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
IPG Graduate Intern
Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Cypress Semiconductor
Sr. IC Product/Test Engineer
Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Cypress Semiconductor
IC Test Engineer
Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Persistent Systems
Intern
Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)