
Rakhi Ravindran
• Design Frames using different CAD flows to enhance development of efficient and quality Products. • Comfortable in using Unix...
Bengaluru, Bengaluru, India
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Rakhi Ravindran’s Emails [email protected]
Rakhi Ravindran’s Phone Numbers 1408956****
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Rakhi Ravindran’s Location Bengaluru, Bengaluru, India
Rakhi Ravindran’s Expertise • Design Frames using different CAD flows to enhance development of efficient and quality Products. • Comfortable in using Unix commands, automated tools like Cadence Mask Compose & K2_Viewer for scribe building. • Understanding of the frame array pattern generation using the FRAME PLANNER Program to get the possible array pattern options. • Experienced in building New and Revised Frames along with the basic knowledge on RSA Frames. • Familiar with the Fab Structures used for lithography, metrology, polishing and step sizing which are placed for producing high quality Frame. • Designed layouts for the Fab Structures such as stepper/scanner alignment marks using tools Cadence IC5 (ICFB) and is proficient in PhysVer using Calibre DRV, RVE. • Experience in IC verification methodologies like DRC, CLDRC, compatibility rules and creating Waivers on both the Drawn data and Mask Data. • Clear idea on the Fundamentals of Semiconductor Fabrication Process/IC manufacturing. • Regular interactions between Product Engineering, Release Team to deliver Premium Products. • Skilled to communicate and work with a cross-geographic, multicultural global teams from Penang, Austin and Kentucky effectively.
Rakhi Ravindran’s Current Industry Infineon Technologies
Rakhi
Ravindran’s Prior Industry
Infineon Technologies
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Sreepathy Institute Of Management And Technology
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Rv Vlsi Vlsi And Embedded Systems Design Center
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Work Experience

Infineon Technologies
Senior Engineer Frame Design
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Rv Vlsi Vlsi And Embedded Systems Design Center
Trainee
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Sreepathy Institute Of Management And Technology
Assistant Professor
Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Senior Engineer Frame Design
— Present