
Ramakrishna Pothuri
Good knowledge and experience of ASIC backend implementation Worked on the multimillion chips and technology nodes of 10nm,... | Bengaluru, Karnataka, India
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Ramakrishna Pothuri’s Location Bengaluru, Karnataka, India
Ramakrishna Pothuri’s Expertise Good knowledge and experience of ASIC backend implementation Worked on the multimillion chips and technology nodes of 10nm, 12FFC, 14nm, 22FDX and 28nm Hands on Experience on multiple industry Tools, ICC, Innovus, PT, DC, Genus, Redhawk, Calibre, Spyglass and Spice Strong Hands On Experience in “Netlist to GDSII of Blocks, IP’s and CPU’s which includes Synthesis, timing constraint generation, Floor planning, Power planning, Clock Tree Synthesis, Place and Route, Extraction, STA, IR/Crosstalk and Noise analysis, closing DRC and LVS issues, EM and Signal EM Flow development to avail of latest enhancements in implementation tools Working with the different Teams (PV, PI, IO and SoC) and also with different time zone across globe Knowledge and experience in Custom place and route for the special macros/Effuse etc Good Experience and Knowledge on Low Power Design Techniques Provide Technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful Project outcomes Independent, Self-driven, good team player and Mentored Physical design engineers
Ramakrishna Pothuri’s Current Industry Intel
Ramakrishna
Pothuri’s Prior Industry
Intel
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Work Experience

Intel
Engineering Manager
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Soc Design Engineer
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Mediatek
Senior Engineer
Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Structural Design Engineer
Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Engineer
Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)