
Richard Miller
I have worked in adult education for most of my career. I have taught classes in Calculus, remedial... | Portland, Oregon Metropolitan Area, United States
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Richard Miller’s Emails ri****@sj****.edu
Richard Miller’s Phone Numbers No phone number available.
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Richard Miller’s Location Portland, Oregon Metropolitan Area, United States
Richard Miller’s Expertise I have worked in adult education for most of my career. I have taught classes in Calculus, remedial math, Statistics, Perl, TCL, and Python programming, and basic electronics. I have over ten years experience in hardware design and verification in the networking industry. During this time I have held positions of individual contributor, technical lead and engineering manager, giving me a broad range of knowledge in design automation and software tools. I also have a background in adult education, quality engineering and statistical data analysis. I have a BS degree in Electrical Engineering and a MS degree in Mathematics where I specialized in geometric algebra. Core Qualifications • Engineering management – Team building, mentoring, conflict resolution • Hardware design – FPGA design with Verilog RTL • Hardware verification – Specman, System Verilog, OVM/UVM • Design automation – Perl, Tcl, Expect, Python, C++, Matlab • Networking protocols – IEEE 802.3, Fibre Channel, I2C, SPI, etc. • Quality engineering – Statistical data analysis, R, RS/1, SPC • Adult education – Mathematics, Programming, Electronics • Geometric algebra – Computer graphics/vision, robotics
Richard Miller’s Current Industry Self Employed
Richard
Miller’s Prior Industry
Digital Equipment
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Cisco
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San Jose State University
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Xtremeeda
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Portland Community College
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Northwest Logic A Rambus
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Firstpass Engineering
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Self Employed
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Work Experience

Self Employed
Retired
Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Firstpass Engineering
Principal Engineer
Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Northwest Logic A Rambus
Senior Verification Engineer
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Portland Community College
Calculus Instructor
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Xtremeeda
Senior Verification Consultant
Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Graduate Student
Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Graduate Teaching Assistant
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Cisco
Technical Lead, Hardware Design
Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Cisco
Hardware Engineering Manager, Design Verification
Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Cisco
Hardware Engineer, ASIC and FPGA Functional Verification
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Digital Equipment
Principal Quality Engineer
Sun Jan 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time)
Digital Equipment
Principal Software Engineer
Thu Jan 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time)