
Saket Siddheshwar
As a Sr. SLT Product Development Engineer at NVIDIA, I work on system level testing of cutting-edge graphics... | Santa Clara, California, United States
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Saket Siddheshwar’s Emails ss****@qu****.com
Saket Siddheshwar’s Phone Numbers 1858651****
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Saket Siddheshwar’s Location Santa Clara, California, United States
Saket Siddheshwar’s Expertise As a Sr. SLT Product Development Engineer at NVIDIA, I work on system level testing of cutting-edge graphics and computing products. I leverage my expertise in product testing, software development, and automated test equipment (ATE) to ensure the quality and performance of NVIDIA's products. Before joining NVIDIA, I was a Sr. RF Test Development Engineer at Qualcomm, where I led the product test development for RFFE modules on Advantest 93k platform. I handled end-to-end projects from NPI to CS deliverable, interacting with teams from product, design, systems, both within USA and offshore. I also developed various test methods and software in Java and Python, and performed board level design and yield analysis. I hold a Master's degree in Electrical and Computer Engineering from UC Irvine, where I gained hands-on experience in RFIC and PCB design, optimization, verification, and productization through internships at Qualcomm and Broadcom. I also acquired multiple certifications in Python programming from Coursera, and learned various EDA tools, HDL, and operating systems. I am passionate about product testing and development, and I always seek to learn new skills and technologies to enhance my competencies. I value collaboration, innovation, and quality in my work, and I strive to contribute to the success of my team and organization.
Saket Siddheshwar’s Current Industry Nvidia
Saket
Siddheshwar’s Prior Industry
Advanced Energy
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Uc Irvine
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Qualcomm
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Broadcom
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Nvidia
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Work Experience

Nvidia
Sr. SLT(System Level Test) Product Development Engineer
Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Sr. RF Test Development Engineer
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
RF DVT Engineering Intern
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Analog Design and Characterization Intern
Sat Jun 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Uc Irvine
Graduate Student Researcher
Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Uc Irvine
Graduate Teaching Assistant
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Uc Irvine
Graduate Reader in Electrical and Computer Science Department
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Advanced Energy
Testing Analyst
Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)