Saransh Choudhary saransh.choudhary@intel.com & | • Experience in RTL Design and FE Signoff for mixed signal IPs and SoCs ; additionally, with very fundamental knowledge of Synthesis, LEC and STA • EDA tools : VCS/Verdi, Spyglass, Design Compiler, Conformal and Primetime • Hardware description languages : Verilog, System Verilog • Scripting languages : Shell, Tcl and Perl

Saransh Choudhary

• Experience in RTL Design and FE Signoff for mixed signal IPs and SoCs ; additionally, with very fundamental...

Intel, NO 17, India

*50 free lookup(s) per month.

No credit card required.

Saransh Choudhary’s Emails [email protected]

Saransh Choudhary’s Phone Numbers No phone number available.

Social Media

Saransh Choudhary’s Location Intel, NO 17, India

Saransh Choudhary’s Expertise • Experience in RTL Design and FE Signoff for mixed signal IPs and SoCs ; additionally, with very fundamental knowledge of Synthesis, LEC and STA • EDA tools : VCS/Verdi, Spyglass, Design Compiler, Conformal and Primetime • Hardware description languages : Verilog, System Verilog • Scripting languages : Shell, Tcl and Perl

Saransh Choudhary’s Current Industry Intel

Saransh Choudhary’s Prior Industry
Intel

Not the Saransh Choudhary you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Intel

Mixed Signal Logic Design Engineer

Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Soc Design Engineer

Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Undergraduate Technical Intern

Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Soc Design Engineer

— Present

Skills

Languages

FAQ About Saransh Choudhary

Saransh Choudhary is located at
Intel, NO 17, India

Saransh Choudhary is a
• Experience in RTL Design and FE Signoff for mixed signal IPs and SoCs ; additionally, with very fundamental knowledge of Synthesis, LEC and STA • EDA tools : VCS/Verdi, Spyglass, Design Compiler, Conformal and Primetime • Hardware description languages : Verilog, System Verilog • Scripting languages : Shell, Tcl and Perl Intel

Saransh Choudhary currently works in the
Intel

Saransh Choudhary specializes in
• Experience in RTL Design and FE Signoff for mixed signal IPs and SoCs ; additionally, with very fundamental knowledge of Synthesis, LEC and STA • EDA tools : VCS/Verdi, Spyglass, Design Compiler, Conformal and Primetime • Hardware description languages : Verilog, System Verilog • Scripting languages : Shell, Tcl and Perl