
Sean Hart
Strong skills in architecture, analysis, problem-solving, ASIC/FPGA design and leadership. Adept at analyzing complex problems and mapping solutions,...
New York City Metropolitan Area, New York City Metropolitan Area, United States
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Sean Hart’s Emails [email protected]
Sean Hart’s Phone Numbers No phone number available.
Social Media
Sean Hart’s Location New York City Metropolitan Area, New York City Metropolitan Area, United States
Sean Hart’s Expertise Strong skills in architecture, analysis, problem-solving, ASIC/FPGA design and leadership. Adept at analyzing complex problems and mapping solutions, modelling, defining system architecture, performance, and design requirements, and leading team to completion. Understand databases and tool flows required to maintain quality. Successfully taped out and brought up multiple SOCs. Areas of expertise include: system data flows system bandwidth analysis analytical and simulation-based modelling power-performance-area (PPA) and trade-offs memory systems processor architecture interrupt connectivity Image processing / ISP interconnect specification clock/PLL plan debug plan IP configurations networking automotive safety (FuSa, ISO26262) MIPI Ethernet
Sean Hart’s Current Industry Marvell Technology
Sean
Hart’s Prior Industry
Control Resources
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Fujitsu Network Communications
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Jedai Broadband Networks
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Qualcomm
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Light
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Marvell Technology
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Work Experience

Marvell Technology
Principal Engineer
Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Light
Principal Engineer
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Principal Engineer
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Jedai Broadband Networks
Senior Design Engineer
Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Fujitsu Network Communications
Senior Design Engineer
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)
Control Resources
Senior Design Engineer
Wed Jan 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)