[email protected] & No phone number available.

Seema Jain

Leading a team of high performing engineers, doing Tapeout in latest technology (7nm/16nm finfet, 28nm), I have gained... | Bengaluru, Karnataka, India

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Seema Jain’s Emails [email protected]

Seema Jain’s Phone Numbers No phone number available.

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Seema Jain’s Location Bengaluru, Karnataka, India

Seema Jain’s Expertise Leading a team of high performing engineers, doing Tapeout in latest technology (7nm/16nm finfet, 28nm), I have gained expertise in - Circuit Design (Architecture/Simulation/Layout) - SOC/IP Deliveries across various geographies - 3rd party IP engagements including technical evaluations of multiple vendors (suppliers of foundation IPs), SOWs, conducting reviews, tracking deliverables etc - Management, technical and organization expertise in various semiconductor design operations in Infineon, Lantiq, client design ( TI and Qualcomm ) - Hands-on Domain expertise : Chip Implementation (synthesis-to-GDS), transistor level circuit design, Physical Verification, Understanding of Backend complexities - Interaction with multiple foundries like TSMC, IBM, Chartered and ST Foundries (Crolles, Rousse and Phoenix) for deployment of new Technology and Solution - Proliferating new Technologies and Solutions - Driving innovation, which resulted in two US granted Patent ( Id 7,356,746 & 7,483,289 ) Possess valuable experience on operating style of a semiconductor Product Company, EDA and Design Service Company

Seema Jain’s Current Industry Western Digital

Seema Jain’s Prior Industry
Stmicroelectronics | Infineon Technologies | Lantiq | Mirafra Technologies | Western Digital

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Work Experience

Western Digital

Director

Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Western Digital

Senior Technical Manager, Mixed Signal Ip Layout And Flow

Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Mirafra Technologies

Director Engineering, Physical Design

Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Mirafra Technologies

Senior Manager

Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Lantiq

Sr Staff Engineer, Physical Design

Sun Nov 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Infineon Technologies

Staff Engineer

Sat Nov 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

Infineon Technologies

Senior Design Engineer

Sun Aug 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Stmicroelectronics

Design Engineer, Sram Design

Tue Jun 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

Seema Jain Email Addresses

[email protected] Email

Seema Jain Phone Number

No phone number available. Phone number

FAQ About Seema Jain

Seema Jain is located at
Bengaluru, Karnataka, India

Seema Jain is a
Leading a team of high performing engineers, doing Tapeout in latest technology (7nm/16nm finfet, 28nm), I have gained expertise in - Circuit Design (Architecture/Simulation/Layout) - SOC/IP Deliveries across various geographies - 3rd party IP engagements including technical evaluations of multiple vendors (suppliers of foundation IPs), SOWs, conducting reviews, tracking deliverables etc - Management, technical and organization expertise in various semiconductor design operations in Infineon, Lantiq, client design ( TI and Qualcomm ) - Hands-on Domain expertise : Chip Implementation (synthesis-to-GDS), transistor level circuit design, Physical Verification, Understanding of Backend complexities - Interaction with multiple foundries like TSMC, IBM, Chartered and ST Foundries (Crolles, Rousse and Phoenix) for deployment of new Technology and Solution - Proliferating new Technologies and Solutions - Driving innovation, which resulted in two US granted Patent ( Id 7,356,746 & 7,483,289 ) Possess valuable experience on operating style of a semiconductor Product Company, EDA and Design Service Company Western Digital

Seema Jain currently works in the
Western Digital

Seema Jain specializes in
Leading a team of high performing engineers, doing Tapeout in latest technology (7nm/16nm finfet, 28nm), I have gained expertise in - Circuit Design (Architecture/Simulation/Layout) - SOC/IP Deliveries across various geographies - 3rd party IP engagements including technical evaluations of multiple vendors (suppliers of foundation IPs), SOWs, conducting reviews, tracking deliverables etc - Management, technical and organization expertise in various semiconductor design operations in Infineon, Lantiq, client design ( TI and Qualcomm ) - Hands-on Domain expertise : Chip Implementation (synthesis-to-GDS), transistor level circuit design, Physical Verification, Understanding of Backend complexities - Interaction with multiple foundries like TSMC, IBM, Chartered and ST Foundries (Crolles, Rousse and Phoenix) for deployment of new Technology and Solution - Proliferating new Technologies and Solutions - Driving innovation, which resulted in two US granted Patent ( Id 7,356,746 & 7,483,289 ) Possess valuable experience on operating style of a semiconductor Product Company, EDA and Design Service Company

Seema Jain speaks the following languages:
No languages available.

Seema Jain has prior experience in the following industries:
Western Digital , Mirafra Technologies , Mirafra Technologies , Lantiq , Infineon Technologies , Infineon Technologies , Stmicroelectronics

Seema Jain has the following professional experience:
Western Digital , Western Digital , Mirafra Technologies , Mirafra Technologies , Lantiq , Infineon Technologies , Infineon Technologies , Stmicroelectronics .