
Senthil Renganathan
18yrs of experience in the EDA industry. Specialties: Developing Automation Framework on End to End System can be FPGAASIC... | Bengaluru, Karnataka, India
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Senthil Renganathan’s Emails re****@xi****.com
Senthil Renganathan’s Phone Numbers No phone number available.
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Senthil Renganathan’s Location Bengaluru, Karnataka, India
Senthil Renganathan’s Expertise 18yrs of experience in the EDA industry. Specialties: Developing Automation Framework on End to End System can be FPGAASIC Validation platform using Perl, Python, Tcl , Shell and Regression utility such as Jenkins/Cronjob and Version Control repository such as Perforce & Git and Linux compute farms such as LSF/Netbatch.
Senthil Renganathan’s Current Industry Intel
Senthil
Renganathan’s Prior Industry
Intel
|
Tenet Iit Madras
|
Poseidon Design Systems
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Cmc
|
Xilinx
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Work Experience

Intel
System Validation Engineer
Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Design Automation Engineer
Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Design Engineer Section Manager
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Senior Design Engr
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Design Engineer
Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Cmc
IT Engineer
Fri Dec 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Poseidon Design Systems
Member of Technical Staff
Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Tenet Iit Madras
Proj Associate
Sun Aug 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
System Validation Engineer
— Present