
Seung Bae
DRAM Design(DDR5/LPDDR5/GDDR6) NAND Flash Design High speed DRAM interface design - DLL/PLL, clocking, low noise single ended signaling techniques Low power... | South Korea
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Seung Bae’s Emails [email protected]
Seung Bae’s Phone Numbers No phone number available.
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Seung Bae’s Location South Korea
Seung Bae’s Expertise DRAM Design(DDR5/LPDDR5/GDDR6) NAND Flash Design High speed DRAM interface design - DLL/PLL, clocking, low noise single ended signaling techniques Low power equalization for high speed interface - DFE, linear equalizer, integrating DFE Analog circuit design - Regulator, reference generator, temperature sensor Next generation memory architecture DRAM core analog circuit design 50+ technical papers and 70+ US patents Presenting author of 4 ISSCC and 1 VLSI
Seung Bae’s Current Industry 삼성전자
Seung
Bae’s Prior Industry
Samsung Electronics
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삼성전자
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Massachusetts Institute Of Technology
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Work Experience

삼성전자
Vice President
Sat Dec 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Massachusetts Institute Of Technology
Visiting Scientist
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
삼성전자
Principal Engineer
Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung Electronics
Senior Engineer
Thu Sep 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)