
Shaji Yusuf
I started my career in high-speed board design, shifted to firmware development, and then to Operating System internals... | Bengaluru, Karnataka, India
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Shaji Yusuf’s Location Bengaluru, Karnataka, India
Shaji Yusuf’s Expertise I started my career in high-speed board design, shifted to firmware development, and then to Operating System internals for Windows and Linux. At Intel, I started my career as a post-silicon validation engineer in the Validation Engineering team in India, focusing on test content development and system debug of Intel's multi-core / socket server Xeon processors. While working in this role, I got the opportunity to work on RTL full-chip verification and the development of key DFD capabilities. My fascination with system level simulation models led me to take up a lead role in Intel's system level simulation model development team in Chandler AZ, US. This included the development of bus functional model interfaces driving Intel's hybrid system-level emulation models and the development of Uncore and IO Controller-Hub models in C++. In the above roles, I got the opportunity to make key contributions to the development of 64 bit Intel Xeon Server CPUs used in HPC and data centre installations across the globe. I also got the privilege to work on the development of last two generations of Itanium processors, codenamed Tukwila and Poulson, that went into leading supercomputers across the world. The system-level simulation models we developed enabled large NUMA servers running thousands of CPUs. After working at Intel in the above mentioned roles, I went on to found a start-up technology company in the field of virtualization and later rejoined Intel's development center in India to work with a team that develops UEFI silicon reference code for Intel's Xeon CPUs. The primary responsibilities in this role included the development of UEFI-compliant firmware for CPU initialization and executing that on system-level emulation models. System-level emulation models and hybrid system-level emulation models form the primary test and validation vehicles for full-chip RTL validation teams. In my current role as a silicon firmware development engineer within Intel's Software and Advanced Technology Group, I have led the BIOS development and system-level emulation efforts for multiple generations of Intel's Xeon D (optimized for density), Xeon SP (scalable processor), and Xeon AP (advanced performance) platforms. I have received multiple awards and recognitions at Intel, including the Distinguished Invention Award and various departmental and divisional-level awards. Apart from my role at Intel, I have also been involved in Linux kernel development, operating system optimization techniques, and I have presented my studies at international conferences and journals.
Shaji Yusuf’s Current Industry Intel
Shaji
Yusuf’s Prior Industry
Caravel Info Systems
|
Hcl Technologies
|
Intel
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Work Experience

Intel
Silicon Firmware Engineer
Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
System Validation Engineer
Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Hcl Technologies
Member of Tech Staff
Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Caravel Info Systems
Senior System Engineer
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)