
Shanmuga Vignesh
Summary: Analog/Mixed-Signal IC Design Engineer with 7+ years of relevant professional experience. Skilled in the design of High-Performance Bandgap... | Bengaluru, Bengaluru, India
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Shanmuga Vignesh’s Emails vi****@mi****.com
Shanmuga Vignesh’s Phone Numbers No phone number available.
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Shanmuga Vignesh’s Location Bengaluru, Bengaluru, India
Shanmuga Vignesh’s Expertise Summary: Analog/Mixed-Signal IC Design Engineer with 7+ years of relevant professional experience. Skilled in the design of High-Performance Bandgap References, High Bandwidth Low Drop-out Voltage Regulators, Relaxation Oscillators, ADCs & DACs, Charge Pumps, Temperature Sensors, POR circuits, Low Offset Comparators, High Speed Transmitters & VREF generators. Knowledged in layout-aware nano-power design techniques in BiCMOS & high-end TSMC processes. A highly motivated, resourceful design professional who embraces teamwork. Technical Skills: • Cadence Virtuoso XL, Cadence Spectre, Mentor Calibre, Cadence SKILL/OCEAN Programming, Verilog/VHDL, Python. • Analog IC Design, Mixed-signal verification, Floorplanning, ESD circuits, and Post-silicon bring-up. Accomplishments: • Analog circuits design in 9 different ICs, for Parallel Memory Interface, Supervisory, RF Transceiver, and Real-Time Clock Applications. • Successful & Timely First Silicon Experience in all 9 ICs (25 Analog blocks).
Shanmuga Vignesh’s Current Industry Micron Technology
Shanmuga
Vignesh’s Prior Industry
College Of Engineering Guindy
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Bharti Airtel
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Maxim Integrated
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Micron Technology
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Work Experience

Micron Technology
Staff Analog Design Engineer
Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Micron Technology
Senior Analog Design Engineer
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Maxim Integrated
Member of Technical Staff, IC Design
Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Maxim Integrated
Associate Member of Technical Staff, IC Design
Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Bharti Airtel
Young Technical Leader, Network
Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
College Of Engineering Guindy
Undergraduate Student Researcher - Integrated Systems Laboratory
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)