
Shouwen Fu
I am a trailblazer. My education started in the field of Computer Science, and has evolved to the... | Greater Sacramento, Greater Sacramento, United States
*50 free lookup(s) per month.
No credit card required.
Shouwen Fu’s Emails sh****@in****.com
Shouwen Fu’s Phone Numbers No phone number available.
Social Media
Shouwen Fu’s Location Greater Sacramento, Greater Sacramento, United States
Shouwen Fu’s Expertise I am a trailblazer. My education started in the field of Computer Science, and has evolved to the current work I do in SOC backend convergence. I have been working in the CPU / Graphics / SOC timing and floorplaning for the last 10+ years. My expertise ranges from floorplanning, netlist manipulation, to timing closure. One of my greatest pleasures is walking into a store and seeing consumers purchase the products that I had a role in creating. Cutting edge technology. How cool is that? I have extensive background in backend convergence from project definition, methodology trailblazing, through execution convergence. As a cluster level and product level timing owner, I love to work with large design teams across many design functions from RTL / DFT to physical design. Better. Faster. Smaller. I have worked with teams that taped-in several CPU projects at 45nm, 28nm, and 14nm, working at different timing corners and process variation. As the feature size get smaller, all design rules are getting stranger every day. Hey, 10nm and 7nm are around the corner! Over the course of my career, i have developed great scripting skill in handling design flow and infrastructure through PERL / Python / TCL / HTML / Javascript. I welcome the opportunity to exchange ideas, share information, and network. I can be reached at [email protected] or 916.218.0317.
Shouwen Fu’s Current Industry Intel
Shouwen
Fu’s Prior Industry
Intel
Not the Shouwen Fu you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Intel
Senior Graphic Hardware Engineer
Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Senior Component Design Engineer
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Component Design Engineer
Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Automation Engineer
Mon Jan 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)