Sj Jeong

Sj Jeong

Based in Korea, More than 25 years of experience in semiconductor assembly & package engineering, new package development... | South Korea

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Work Experience

Intel

Packaging Engineer

Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Xilinx

Sr.Staff Assembly Engineer & Subcontrator Manager

Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Xilinx

Staff Engineer & Subcontractor Manager

Fri Jul 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Xilinx

Sr.Staff Packaging Engineer & Subcontractor Manager

Wed Dec 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Xilinx

Senior Packaging Engineer

Wed Dec 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)

Stats Chippac

Senior Engineer

Sat Nov 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)

Sk Hynix

Process Engineer

Sun Nov 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

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