
Soyeb Khanusiya
Working as Principal Verification Engineer in Cirrus Logic Edinburgh, I am involved in functional and formal verification... | Cirrus Logic, Edinburgh, United Kingdom
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Soyeb Khanusiya’s Emails so****@ci****.com
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Soyeb Khanusiya’s Location Cirrus Logic, Edinburgh, United Kingdom
Soyeb Khanusiya’s Expertise Working as Principal Verification Engineer in Cirrus Logic Edinburgh, I am involved in functional and formal verification of Audio mix signal ASIC, Sub-Systems and IP's using System Verilog Universal Verification Methodology and c++ based verification environment. Specialties: Systm Verilog,UVM, Verilog, SystemC , C/C++, Functional Verification, Formal Verification, AMBA AHB,APB,AXI, MIPI CSI, IDP,ISB, RTL Debuging, coverage analysis, AES, processor verification, RISC-V
Soyeb Khanusiya’s Current Industry Imagination Technologies
Soyeb
Khanusiya’s Prior Industry
Stmicroelectronics
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Rambus
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Cirrus Logic
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Imagination Technologies
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Work Experience

Imagination Technologies
Principal Hardware Engineer
Mon May 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cirrus Logic
Principal Verification Engineer
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Cirrus Logic
Senior Verification Engineer
Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Rambus
SMTS-II ASIC Verification Engineer - Verification Lead
Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Rambus
SMTS ASIC Verification Engineer
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Rambus
MTS ASIC Verification Engineer
Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Senior Design Engineer
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Design Engineer
Sat Sep 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Internship
Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)