Subhas Bhat

FAQ About Subhas Bhat

• What is Subhas Bhat's address?

  Subhas Bhat is located at
  Bengaluru, Karnataka, India

• What is Subhas Bhat's job title?

  Subhas Bhat is a
  Ten plus years of Experience in VLSI ASIC (Application Specific Integrated Circuits)Design Verification(Pre-Silicon) Engineering. SoC and Subsystem level PCIe End to End Verification of RPs, EPs and Switches... Key Areas: - Enumeration - PCIe PM/ASPM - PCIe AER - MAC/PIPE Loopback and Compliance - DMA and other PCIe Traffics SoC and IP level ASIC Design Verification using System Verilog VMM,OVM and UVM Methodologies. Worked SAS/SATA Core verification using SV-UVM Methodology. Worked on PCIe Gen1/Gen2/Gen3/Gen4 Switch(PCIe-Fabric) Verification activity in SV-VMM Environment[CSRs,Resets,Enumeration,PHY etc...]. Chip Bring-up using Serial Boot Loaders like Flash,EEPROM etc.. Worked on Test Bench development and Test case development for Data Integrity logic verification in SV-VMM environment. Worked on Intel's USB 2.0 PHY verification project in SV-OVM environment. Worked on Intel's SOC(System on Chip) Verification project in SV-OVM environment. Worked on basic JTAG verification. Specialties: Tool used: Cadance NCsim,Synopsis VCS,Mentor's ModelSim and Xilinx ISE. Hardware langauages:Verilog and basic VHDL High Level Verification Language (HVL) : System Verilog. Verision Controls Used: Git,SVN,CVS Methodology : OVM,VMM,UVM Basic scripting using PERL and Shell. Operating Systems: Unix and Windows. Intel

• What industry does Subhas Bhat currently work in?

  Subhas Bhat currently works in the
  Intel

• What is Subhas Bhat's area of expertise?

  Subhas Bhat specializes in
  Ten plus years of Experience in VLSI ASIC (Application Specific Integrated Circuits)Design Verification(Pre-Silicon) Engineering. SoC and Subsystem level PCIe End to End Verification of RPs, EPs and Switches... Key Areas: - Enumeration - PCIe PM/ASPM - PCIe AER - MAC/PIPE Loopback and Compliance - DMA and other PCIe Traffics SoC and IP level ASIC Design Verification using System Verilog VMM,OVM and UVM Methodologies. Worked SAS/SATA Core verification using SV-UVM Methodology. Worked on PCIe Gen1/Gen2/Gen3/Gen4 Switch(PCIe-Fabric) Verification activity in SV-VMM Environment[CSRs,Resets,Enumeration,PHY etc...]. Chip Bring-up using Serial Boot Loaders like Flash,EEPROM etc.. Worked on Test Bench development and Test case development for Data Integrity logic verification in SV-VMM environment. Worked on Intel's USB 2.0 PHY verification project in SV-OVM environment. Worked on Intel's SOC(System on Chip) Verification project in SV-OVM environment. Worked on basic JTAG verification. Specialties: Tool used: Cadance NCsim,Synopsis VCS,Mentor's ModelSim and Xilinx ISE. Hardware langauages:Verilog and basic VHDL High Level Verification Language (HVL) : System Verilog. Verision Controls Used: Git,SVN,CVS Methodology : OVM,VMM,UVM Basic scripting using PERL and Shell. Operating Systems: Unix and Windows.

• Which languages does Subhas Bhat speak? 

  Subhas Bhat speaks the following languages:
  No languages available.

• Which industries has Subhas Bhat previously worked in?   

  Subhas Bhat has prior experience in the following industries:
  Broadcom , Sicon Design Technologies , Wipro Technologies

• What is Subhas Bhat’s work experience?  

  Subhas Bhat has the following professional experience:
  Intel , Broadcom , Sicon Design Technologies , Wipro Technologies , Intel .

• How can I find Subhas Bhat on LinkedIn?  

  You can view Subhas Bhat’s
  LinkedIn profile at LinkedIn URL.

• What are Subhas Bhat’s work email addresses?  

  Subhas Bhat’s work email addresses are
  [email protected] .

• What company does Subhas Bhat work for?  

  Subhas Bhat works at
  Intel