
Sudhakar Eswaran
I have about 18 yrs of experience in the VLSI/FPGA domain. Have valid H1B visa till Dec'2017. I have... | Bengaluru, Karnataka, India
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Sudhakar Eswaran’s Emails su****@wi****.com
Sudhakar Eswaran’s Phone Numbers No phone number available.
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Sudhakar Eswaran’s Location Bengaluru, Karnataka, India
Sudhakar Eswaran’s Expertise I have about 18 yrs of experience in the VLSI/FPGA domain. Have valid H1B visa till Dec'2017. I have good knowledge in the HDL's like Verilog & VHDL I have worked in both system development/design, RTL development, verification/writing test benches/timing verification/VITAL simulation etc and board level testing also I have good exposure to latest EDA tools like ModelSim, Leonardo Spectrum, Xilinx ISE, Altera - Quartus I have good experience in FPGA vendors like Xilinx, Altera I have good exposure to Chipscope, Signal tap, CRO and logical analyzer testing equipments I have done the managing and review of Board level design and verification Aim currently handling a team size of about 4 engineers and had performed as a good project leader for the past 3 yrs which includes project planning, management and project delivery I have good exposure to DO254 standarads Worked on tools like DOORS, PREP and clearQuest
Sudhakar Eswaran’s Current Industry Wipro
Sudhakar
Eswaran’s Prior Industry
Wipro
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V Design
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Seodu Logic
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Samsung Electro Mechanics
|
Einfochips
|
Smartplay Technologies
|
Cyient
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Work Experience

Wipro
Project Manager
Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cyient
Project Manager
Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Smartplay Technologies
Tech Lead
Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Sr. Asic Engineer
Tue Dec 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung Electro Mechanics
Leading Engineer
Thu Apr 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Seodu Logic
Design Engineer
Sat Mar 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
V Design
Design Engineer
Sat May 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro
Project Manager
— Present