
Sudhir Chandel
SoC RTL Design and Implementation with a special focus on PPA optimization and STA sign-off Specialties: Leading the development... | San Jose, California, United States
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Sudhir Chandel’s Location San Jose, California, United States
Sudhir Chandel’s Expertise SoC RTL Design and Implementation with a special focus on PPA optimization and STA sign-off Specialties: Leading the development of SoC products with the multi-site design team from specifications to production SoC Microarchitecture and Implementation possibilities and strategy development for SoC Design Chip Assembly, RTL Design, IP Integration, Low power design & Power analysis Full-Chip Clock/Reset Architecture, Chip operating modes, Chip Power management Full-Chip and Hierarchical Timing Constraints Development Full-Chip STA Sign-off Experience collaborating with international teams Experience mentoring junior team members and overseeing their work Protocols: PCIe, WLAN (802.11) MAC, SATA I/II, DDR, Audio, Nand Flash, eMMC and SDIO RTL Coding, Synthesis, EC, Power analysis, IR/EM and STA Sign-off
Sudhir Chandel’s Current Industry Synaptics
Sudhir
Chandel’s Prior Industry
Dcm Technologies
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Nuelight
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Marvell Semiconductor
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Synaptics
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Work Experience

Synaptics
Sr. Manager, ASIC Design Engineering
Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Marvell Semiconductor
Sr. Staff, ASIC Design Engineer
Thu Feb 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Nuelight
Sr. Design Engineer
Mon Aug 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Dcm Technologies
Design Team Lead
Fri Sep 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)