
Sylvain Meliciani
- ASIC/ASSP development from specifications to physical implentation, hardware design (VHDL or Verilog), synthesis, static timing analysis, timing... | Greater Paris Metropolitan Region, Greater Paris Metropolitan Region, France
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Sylvain Meliciani’s Emails sm****@go****.com
Sylvain Meliciani’s Phone Numbers 1415738****
Social Media
Sylvain Meliciani’s Location Greater Paris Metropolitan Region, Greater Paris Metropolitan Region, France
Sylvain Meliciani’s Expertise - ASIC/ASSP development from specifications to physical implentation, hardware design (VHDL or Verilog), synthesis, static timing analysis, timing driven plage&route, emulation and prototyping. System-On-Chip conception, IP integration development and verification. - Verification Methodology development for complex Soc including Network-On-Chip communication structure. Specialties: ASIC or ASSP SoC development Complex SoC with NoC Architecture implementation and Verification Multimedia, Telecommunication and Avionics
Sylvain Meliciani’s Current Industry Gopro
Sylvain
Meliciani’s Prior Industry
Texas Instrument
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Sextant Avionique
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Philips Semi Conductor
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Globespan
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Arteris
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Dxo Labs
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Gopro
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Work Experience

Gopro
Principal Engineer
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Dxo Labs
Hardware Verification Leader
Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Arteris
Technical Verification Leader
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Globespan
Verification Engineer
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Philips Semi Conductor
Technical Leader
Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Sextant Avionique
Project Leader
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instrument
Design Engineer
Mon Jan 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)