
Thangavel Swamynathan
• Verification expert On peripheral Interface IP’s • Currently working on Testbech Development for Digital IP's : USB4 2.0 and Gen... | Chennai, Tamil Nadu, India
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Thangavel Swamynathan’s Emails th****@qu****.com
Thangavel Swamynathan’s Phone Numbers 1858651****
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Thangavel Swamynathan’s Location Chennai, Tamil Nadu, India
Thangavel Swamynathan’s Expertise • Verification expert On peripheral Interface IP’s • Currently working on Testbech Development for Digital IP's : USB4 2.0 and Gen T Protocols. • Expertise in verification plan creation for USB/Interface IP Protocols • Responsible for USB3.1 and Host Interface Adapter(HIA), Control Port and Logical Layer Design Verification in USB 4.0 V2. • Responsible for Test Bench Development, Verification of USB IP's for Various QCOM Compute Chipsets. • Working experience on IP Design Verification of USB 2.0/3.0/3.1/3.2/4.0/4.0 v2 protocol. • Experience in working with SOC Team over critical debugs. • Experience in working with Overseas Team over IP development. • Experience in working with pre-silicon Emulation, Post-Silicon Validation Teams over Bring Up and Debug and Performance Simulations.
Thangavel Swamynathan’s Current Industry Qualcomm
Thangavel
Swamynathan’s Prior Industry
Arasan Chip Systems
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L And T Technology Services
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Synopsys
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Qualcomm
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Work Experience

Qualcomm
Sr Staff Engineer
Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Staff Engineer
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Sr Lead Engineer
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Sr R&D Engineer
Tue Mar 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
L And T Technology Services
Senior Engineer
Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Arasan Chip Systems
Verification Engineer
Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)