
Tim Swensen
Product Specialist Engineer for Custom Integrated Circuits Verification team. Former Product Engineer for Analog Fast Spice (AFS)simulator. Previously: 17 years... | Santa Clara, California, United States
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Tim Swensen’s Emails ti****@mentor.com
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Tim Swensen’s Location Santa Clara, California, United States
Tim Swensen’s Expertise Product Specialist Engineer for Custom Integrated Circuits Verification team. Former Product Engineer for Analog Fast Spice (AFS)simulator. Previously: 17 years of digital IC design experience in FPGA companies: Embedded SRAM, volatile and non-volatile security fuses, FPGA routing fabric. Designed in processes down through 20n Circuit design, layout floorplanning, SPICE, Verilog RTL, linting, timing closure, formal verification. Granted four U.S. Patents.
Tim Swensen’s Current Industry Siemens Digital Industries Software
Tim
Swensen’s Prior Industry
Acuson
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Purdue University
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Lattice Semiconductor
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Altera
|
Mentor Graphics
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Siemens Digital Industries Software
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Work Experience

Siemens Digital Industries Software
Product Specialist
Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Siemens Digital Industries Software
Senior Product Engineer, Memory Verification
Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Mentor Graphics
Senior Product Engineer, Memory Verification
Sat Mar 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Altera
Design Engineer, Senior MTS
Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Lattice Semiconductor
Staff Design Engineer
Thu Jun 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Purdue University
Graduate Teaching Assistant
Wed Aug 01 1990 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time)
Acuson
Test Engineer
Wed Jul 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 1990 00:00:00 GMT+0000 (Coordinated Universal Time)