
Vinayak Mahajan
Compact Device Modeling, RF Circuit and Digital Design, Test chip Development, Technology evaluation and benchmarking. Experience in Transistor Technologies... | Irvine, California, United States
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Vinayak Mahajan’s Emails vi****@gl****.com
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Vinayak Mahajan’s Location Irvine, California, United States
Vinayak Mahajan’s Expertise Compact Device Modeling, RF Circuit and Digital Design, Test chip Development, Technology evaluation and benchmarking. Experience in Transistor Technologies - GAAFET, FinFET, Planar Bulk, FDSOI, PDSOI, Silicon Photonics, GaN, GaN-on-Si Expertise: Semiconductor device physics, novel device physics, compact modeling (BSIM, PSP, CMG, IMG, ASM-HEMT), advanced bulk and SOI technologies, FinFETs, non-classical CMOS, noise in devices and circuits, process variation and statistical modeling, compact model parameter extraction, device characterization, process and device simulation (TCAD), circuit simulation (DC, RF, Noise, Transient, Harmonics and IMD, SourcePull, LoadPull), test structure design, layout dependent effects CAD Tool expertise: Cadence Virtuoso, Keysight ADS, MentorCalibre, Synopsys StarRC, Cadence QRC, Electromagnetic simulators- EMX and Momentum, Parameter extraction tools-ICCAP and MBP Scripting expertise: Perl and R.
Vinayak Mahajan’s Current Industry Broadcom
Vinayak
Mahajan’s Prior Industry
University Of Louisiana At Lafayette
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Globalfoundries
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Broadcom
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Work Experience

Broadcom
Principal R&D Hardware Engineer
Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Globalfoundries
Senior Member Of Technical Staff
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Member of Technical Staff - TD Integration Engineering
Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Principal Engineer - TD Integration Engineering
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Senior Engineer - TD Integration Engineering
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Louisiana At Lafayette
TCAD Engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Louisiana At Lafayette
Research Assistant
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)