Vivek Ramnath

FAQ About Vivek Ramnath

• What is Vivek Ramnath's address?

  Vivek Ramnath is located at
  Austin, Texas, United States

• What is Vivek Ramnath's job title?

  Vivek Ramnath is a
  As a student I have been part of many projects at North Carolina State University.Some of them are mentioned below: • Verification of LC3 microcontroller using a fully randomized object oriented framework with constraint random testing. Immediate and concurrent assertions were used to implement the checker of the verification framework. Tool used: System Verilog. • 4 port SRAM layout: Designed the schematic and layout of dual port SRAM in 45nm technology. Unique decoding techniques were studied as part of this project. Tool used: Cadence Virtuoso. • Utterance Matcher: A speech recognition system was designed using Verilog and synthesized successfully in order to exploit the parallelism inherent in the lookup table process. Tool used: Synopsys Design Compiler. • 16-bit RISC processor: A classic five stage pipelined 16- bit RISC processor was designed and synthesized using synopsys(Design Compiler). The processor supported 32 instructions and followed fixed encoding format. • Design of CMOS OP-Amp: A schematic of CMOS op amp using the folded cascode structure which was insensitive to process & temperature variations was designed. Tool used: Analog Artist. • Low power buffer Insertion Algorithm: A unique low power buffer insertion algorithm was developed which was scalable and also comparable to the best solution present. The algorithm was parallelized using Open MP and CUDA and an effective speed up of 5 to 7 was obtained. • Placement of an LSI circuit: A placement algorithm based on simulated annealing using linear ordering was developed in C. The same algorithm was parallelized using CUDA to reduce the time complexity to a factor ’n’. • Cache simulator in C: A cache simulator was designed in C wherein different cache configurations was studied in depth and the parameters that affect in choosing the best cache configuration were evaluated. Specialties: Technical Skills that I have gathered as a student and as an intern: TECHNICAL SKILLS: Languages : C,C++, Verilog, System Verilog, Vera, Tcl/Tk,perl,OpenMP,CUDA. Simulation Tools : Questasim,Modelsim,Ncsim. Synthesis Tools : Synopsys(Design Compiler) & Cadence(RTL Compiler 6.0). DFT Tools : DFTAdvisor,FastScan, MBISTArchitect,BSDArchitect. Static Timing Analysis : Primetime. Formal Verification : Cadence Conformal. Low Power :Scripting in UPF & CPF Apple

• What industry does Vivek Ramnath currently work in?

  Vivek Ramnath currently works in the
  Apple

• What is Vivek Ramnath's area of expertise?

  Vivek Ramnath specializes in
  As a student I have been part of many projects at North Carolina State University.Some of them are mentioned below: • Verification of LC3 microcontroller using a fully randomized object oriented framework with constraint random testing. Immediate and concurrent assertions were used to implement the checker of the verification framework. Tool used: System Verilog. • 4 port SRAM layout: Designed the schematic and layout of dual port SRAM in 45nm technology. Unique decoding techniques were studied as part of this project. Tool used: Cadence Virtuoso. • Utterance Matcher: A speech recognition system was designed using Verilog and synthesized successfully in order to exploit the parallelism inherent in the lookup table process. Tool used: Synopsys Design Compiler. • 16-bit RISC processor: A classic five stage pipelined 16- bit RISC processor was designed and synthesized using synopsys(Design Compiler). The processor supported 32 instructions and followed fixed encoding format. • Design of CMOS OP-Amp: A schematic of CMOS op amp using the folded cascode structure which was insensitive to process & temperature variations was designed. Tool used: Analog Artist. • Low power buffer Insertion Algorithm: A unique low power buffer insertion algorithm was developed which was scalable and also comparable to the best solution present. The algorithm was parallelized using Open MP and CUDA and an effective speed up of 5 to 7 was obtained. • Placement of an LSI circuit: A placement algorithm based on simulated annealing using linear ordering was developed in C. The same algorithm was parallelized using CUDA to reduce the time complexity to a factor ’n’. • Cache simulator in C: A cache simulator was designed in C wherein different cache configurations was studied in depth and the parameters that affect in choosing the best cache configuration were evaluated. Specialties: Technical Skills that I have gathered as a student and as an intern: TECHNICAL SKILLS: Languages : C,C++, Verilog, System Verilog, Vera, Tcl/Tk,perl,OpenMP,CUDA. Simulation Tools : Questasim,Modelsim,Ncsim. Synthesis Tools : Synopsys(Design Compiler) & Cadence(RTL Compiler 6.0). DFT Tools : DFTAdvisor,FastScan, MBISTArchitect,BSDArchitect. Static Timing Analysis : Primetime. Formal Verification : Cadence Conformal. Low Power :Scripting in UPF & CPF

• Which languages does Vivek Ramnath speak? 

  Vivek Ramnath speaks the following languages:
  No languages available.

• Which industries has Vivek Ramnath previously worked in?   

  Vivek Ramnath has prior experience in the following industries:
  Barefoot Networks , Samsung Austin R And D Center , Texas Instruments , Infotech Enterprises America , Infotech Enterprises Ltd Electronics Design Services , Skandsoft Technoliges

• What is Vivek Ramnath’s work experience?  

  Vivek Ramnath has the following professional experience:
  Apple , Barefoot Networks , Samsung Austin R And D Center , Texas Instruments , Infotech Enterprises America , Infotech Enterprises Ltd Electronics Design Services , Skandsoft Technoliges .

• How can I find Vivek Ramnath on LinkedIn?  

  You can view Vivek Ramnath’s
  LinkedIn profile at LinkedIn URL.

• What are Vivek Ramnath’s work email addresses?  

  Vivek Ramnath’s work email addresses are
  [email protected].

• What company does Vivek Ramnath work for?  

  Vivek Ramnath works at
  Apple