Wen-Hsien Chuang

Wen-Hsien Chuang

- Responsible for root cause understanding of inline and end-of-line (EOL) process defects, reliability fails, device performance, circuit... | Portland, Oregon, United States

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Work Experience

Tsmc

Director

Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Engineering Td Manager

Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Failure Isolation/Analysis Technology Development Engineer

Wed Jun 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Engineering Td Manager

— Present

Skills

Languages

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