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Yazdan Torabian

► Digital Logic Design targeted towards FPGA Design in System-Oriented Companies. ☎ (408) 313-2936 /... | San Jose, California, United States

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Yazdan Torabian’s Location San Jose, California, United States

Yazdan Torabian’s Expertise ► Digital Logic Design targeted towards FPGA Design in System-Oriented Companies. ☎ (408) 313-2936 / [email protected] ✱ SENIOR FPGA DESIGN ENGINEER / LOGIC DESIGN ENGINEER / ASIC to FPGA ✱ MS Degree, Electrical Engineering / BS Degree, Computer Engineering / Signal Processing Cert ─ ─ ─ ─ ─ ─ ─ ─ ─ EXCELLENCE IN EXECUTION ─ ─ ─ ─ ─ ─ ─ ─ ─ ► Senior FPGA Design Engineer offering over 10 years’ experience in FPGA design engineering including life-cycle process ownership of specifications, architecture, programming, emulation, verification, maintenance and upgrades. ► Deep analytical, architectural and programming skills; high-level verification languages; and top-tier error-free market ready designs. ► Expert knowledge-level of computer engineering, from vision to analysis, design, validation, and deployment. ► Expertise in Data Security, Consumer Electronic Devices, Semiconductor Testing, and Military Defense FPGA applications. ► Solves complex engineering problems using contemporary engineering principles, methodologies, and tools. ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ TECHNICAL EXPERTISE ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ✱ TECHNICAL SKILLS / DESIGN TOOLS / VALIDATION / PROTOCOLS / PROGRAMMING ✱ FPGA-Design, Logic-Design (RTL: Verilog, System Verilog, VHDL), Xilinx ISE/Vivado; Altera Quartus, DSP48 Block of Xilinx and SerDes, GTH/GTX/GTP of Xilinx and Achronix, Implementation of various Protocols (SAS, SATA, DDR-3, PCI_E, USB 3.0, Ethernet) in the FPGA, SerDes Validation (Jtol), Signal Processing Implementation in the FPGA (Cordic, DDS), BER Design in the FPGA, ASIC Emulation in the FPGA, On-chip Logic Analyzer Implementation, such as Chip-scope, Signal–Tap, Schematic Capture (OrCad ), C++, Perl, AHB Bus, Verification of Large Systems with OVM, Driver Software using C Coding, Embedded Mips Process Debugging with Imagination Tool, Digital Board Design Skills ► Expertise: Sr FPGA Design Engineer / SerDes Validation Engineer / Logic Design Engineer / Hardware Engineer

Yazdan Torabian’s Current Industry Boeing

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Work Experience

Boeing

Senior Fpga Engineer

Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Fpga Engineer

Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Microsoft

Fpga Validation Engineer

Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Palo Alto Networks

Fpga Engineer

Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Northrop Grumman

Senior Fpga Design Engineer

Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Tektronix

Senior Fpga Design Engineer

Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Eagle Seven

Senior Fpga Design Engineer

Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

General Dynamics Mission Systems

Senior Fpga Design Engineer

Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Advantest

Fpga Storage Design Engineer

Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Achronix Semiconductor

Fpga Application / Design Engineer

Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Jdsu

Senior Fpga / Logic Design Engineer

Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Xilinx

Serdes Validation Engineer

Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Quantenna Communications

Asic To Fpga Emulation Engineer

Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Lecroy

Senior Fpga / Logic Design Engineer

Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Boeing

Senior Fpga Engineer

— Present

Skills

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Yazdan Torabian Email Addresses

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ya****@ac****.com Personal Email

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FAQ About Yazdan Torabian

Yazdan Torabian is located at
San Jose, California, United States

Yazdan Torabian is a
► Digital Logic Design targeted towards FPGA Design in System-Oriented Companies. ☎ (408) 313-2936 / [email protected] ✱ SENIOR FPGA DESIGN ENGINEER / LOGIC DESIGN ENGINEER / ASIC to FPGA ✱ MS Degree, Electrical Engineering / BS Degree, Computer Engineering / Signal Processing Cert ─ ─ ─ ─ ─ ─ ─ ─ ─ EXCELLENCE IN EXECUTION ─ ─ ─ ─ ─ ─ ─ ─ ─ ► Senior FPGA Design Engineer offering over 10 years’ experience in FPGA design engineering including life-cycle process ownership of specifications, architecture, programming, emulation, verification, maintenance and upgrades. ► Deep analytical, architectural and programming skills; high-level verification languages; and top-tier error-free market ready designs. ► Expert knowledge-level of computer engineering, from vision to analysis, design, validation, and deployment. ► Expertise in Data Security, Consumer Electronic Devices, Semiconductor Testing, and Military Defense FPGA applications. ► Solves complex engineering problems using contemporary engineering principles, methodologies, and tools. ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ TECHNICAL EXPERTISE ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ✱ TECHNICAL SKILLS / DESIGN TOOLS / VALIDATION / PROTOCOLS / PROGRAMMING ✱ FPGA-Design, Logic-Design (RTL: Verilog, System Verilog, VHDL), Xilinx ISE/Vivado; Altera Quartus, DSP48 Block of Xilinx and SerDes, GTH/GTX/GTP of Xilinx and Achronix, Implementation of various Protocols (SAS, SATA, DDR-3, PCI_E, USB 3.0, Ethernet) in the FPGA, SerDes Validation (Jtol), Signal Processing Implementation in the FPGA (Cordic, DDS), BER Design in the FPGA, ASIC Emulation in the FPGA, On-chip Logic Analyzer Implementation, such as Chip-scope, Signal–Tap, Schematic Capture (OrCad ), C++, Perl, AHB Bus, Verification of Large Systems with OVM, Driver Software using C Coding, Embedded Mips Process Debugging with Imagination Tool, Digital Board Design Skills ► Expertise: Sr FPGA Design Engineer / SerDes Validation Engineer / Logic Design Engineer / Hardware Engineer Boeing

Yazdan Torabian currently works in the
Boeing

Yazdan Torabian specializes in
► Digital Logic Design targeted towards FPGA Design in System-Oriented Companies. ☎ (408) 313-2936 / [email protected] ✱ SENIOR FPGA DESIGN ENGINEER / LOGIC DESIGN ENGINEER / ASIC to FPGA ✱ MS Degree, Electrical Engineering / BS Degree, Computer Engineering / Signal Processing Cert ─ ─ ─ ─ ─ ─ ─ ─ ─ EXCELLENCE IN EXECUTION ─ ─ ─ ─ ─ ─ ─ ─ ─ ► Senior FPGA Design Engineer offering over 10 years’ experience in FPGA design engineering including life-cycle process ownership of specifications, architecture, programming, emulation, verification, maintenance and upgrades. ► Deep analytical, architectural and programming skills; high-level verification languages; and top-tier error-free market ready designs. ► Expert knowledge-level of computer engineering, from vision to analysis, design, validation, and deployment. ► Expertise in Data Security, Consumer Electronic Devices, Semiconductor Testing, and Military Defense FPGA applications. ► Solves complex engineering problems using contemporary engineering principles, methodologies, and tools. ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ TECHNICAL EXPERTISE ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ✱ TECHNICAL SKILLS / DESIGN TOOLS / VALIDATION / PROTOCOLS / PROGRAMMING ✱ FPGA-Design, Logic-Design (RTL: Verilog, System Verilog, VHDL), Xilinx ISE/Vivado; Altera Quartus, DSP48 Block of Xilinx and SerDes, GTH/GTX/GTP of Xilinx and Achronix, Implementation of various Protocols (SAS, SATA, DDR-3, PCI_E, USB 3.0, Ethernet) in the FPGA, SerDes Validation (Jtol), Signal Processing Implementation in the FPGA (Cordic, DDS), BER Design in the FPGA, ASIC Emulation in the FPGA, On-chip Logic Analyzer Implementation, such as Chip-scope, Signal–Tap, Schematic Capture (OrCad ), C++, Perl, AHB Bus, Verification of Large Systems with OVM, Driver Software using C Coding, Embedded Mips Process Debugging with Imagination Tool, Digital Board Design Skills ► Expertise: Sr FPGA Design Engineer / SerDes Validation Engineer / Logic Design Engineer / Hardware Engineer

Yazdan Torabian speaks the following languages:
No languages available.

Yazdan Torabian has prior experience in the following industries:
Boeing , Intel , Microsoft , Palo Alto Networks , Northrop Grumman , Tektronix , Eagle Seven , General Dynamics Mission Systems , Advantest , Achronix Semiconductor , Jdsu , Xilinx , Quantenna Communications , Lecroy

Yazdan Torabian has the following professional experience:
Boeing , Intel , Microsoft , Palo Alto Networks , Northrop Grumman , Tektronix , Eagle Seven , General Dynamics Mission Systems , Advantest , Achronix Semiconductor , Jdsu , Xilinx , Quantenna Communications , Lecroy , Boeing .