Zhi-Hern Loh

Zhi-Hern Loh

Neural Network Accelerator R&D at Expedera Singapore | Singapore

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Work Experience

Expedera

Principal Engineer

Wed Nov 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Silicon Architect, Programmable Solutions Group

Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Modeling Architect, Switch And Fabrics Group

Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Product Architect, Chd

Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Product Architect, Icdg

Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Chip Architect, Networking Division

Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Fulcrum Microsystems

Senior Ic Design Engineer

Sat Sep 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Fulcrum Microsystems

Software Engineer

Fri Oct 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Cornell University

Teaching Assistant For Computer Architecture

Fri Aug 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

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